This invention is directed to microelectronic semiconductor devices and methods of making such devices, and more particularly, to a MESFET device and a process for making said MESFET device.
The history of integrated semiconductor circuit design has been characterized by a trend toward increasing circuit densities. Various technologies have been invented to stimulate this trend. For example, transistor-transistor logic, TTL, was standard in digital equipment for a long time but has given way in many areas to N-channel MOS logic circuits because of their superiority in speed power product, packing density and ease of device fabrication. For these reasons devices fabricated using these technologies are finding application primarily in memory and microprocessor circuits. The MESFET is another device that offers many of the advantages of the N-channel MOS technology without some of its disadvantages. It's primary application will also be in digital technology such as memory and microprocessor type circuits.
One of the problems with N-channel MOS devices is that when they are scaled down in size the gate oxide thickness must be scaled down accordingly. This creates a problem because it is very difficult to fabricate thin silicon oxides that are free from pinholes. If there is a pinhole in one of the gate oxides there will be a gate to channel short and consequently a device failure. Since there are thousands of gate oxide areas on a typical N-channel MOS memory of microprocessor this problem can be very serious.
In copending application, Ser. No. 6842 filed herewith by Darley et al, a MESFET device is disclosed which solves many of the problems with the N-channel MOS silicon gate integrated circuits. With the continuing trend toward higher packing densities the MESFET device described in the above mentioned copending application is not going to be satisfactory for future design needs. There are too many alignment tolerances which restrict chip size that must be allowed for in the device design. These tolerances also limit device performance by increasing the source to drain series resistance.
It is a principal object of this invention to provide an improved MESFET device which is useful in the design of high density digital logic circuits and a method for making said device. Another object is to provide an improved MESFET device with high packing density and low source to drain series resistance.